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VeriFlow-CC

Claude Code-driven RTL design pipeline automating chip design from architecture to synthesis using stateful LLM orchestration and behavioral verification.

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What It Does

VeriFlow-CC is an RTL (Register-Transfer Level) design automation pipeline that treats Claude Code as the orchestration brain. It automates the entire chip design workflow from functional specification through hardware synthesis, eliminating manual handoffs between design stages.

How It Works

The pipeline runs in four sequential stages:

  1. Spec & Golden Model — Generates formal specifications and a reference Python implementation from your requirements
  2. RTL Code Generation — Uses AI sub-agents to synthesize Verilog modules in parallel, following strict coding patterns
  3. Verify & Fix — Runs simulations (iVerilog/cocotb) with automatic error detection and recovery
  4. Lint & Synthesis — Validates code quality and synthesizes to gates using Yosys

State persists to JSON across all stages, allowing recovery after session restarts. The pipeline includes common pitfall detection (7 typical Verilog mistakes) and a failure feedback loop that injects previous errors into the next code generation retry.

Use Cases

  • Rapid prototyping of digital designs without manual RTL coding
  • Education — Learn RTL design patterns and verification flows
  • Hardware teams — Accelerate initial RTL generation for design review cycles
  • Reference implementation validation through golden models

Who Benefits

Design teams, hardware engineers, and product managers evaluating chip design automation. Works best for behavioral RTL designs with clear functional specifications and timing constraints.

Frequently asked questions

How do I install VeriFlow-CC?
Clone the repository and run `python install.py`. This installs the skill, sub-agents, and helper scripts to `~/.claude/`. No pip dependencies required. Uninstall with `python install.py --uninstall`.
What files do I need to start a design?
At minimum, `requirement.md` describing what the design does. Optionally add `constraints.md` (timing/area/power), `design_intent.md` (architecture preferences), and `context/` folder with reference materials. Missing optional files trigger targeted clarification questions.
What's a golden model and why do I need one?
The golden model is a cycle-accurate Python reference implementation generated in Stage 1. It serves as the source of truth for comparing simulation outputs and generating test vectors. The pipeline uses it to detect timing bugs and initialization errors.
How does error recovery work?
When simulation fails, the pipeline classifies the bug (computation error, timing offset, or initialization), creates a concise failure summary, and injects it into the next code generation retry. This focuses the AI on the exact divergence before broader rewrites. You get 3 retry attempts per stage.
Can I use cocotb for simulation?
Yes. VeriFlow-CC prefers cocotb when available because it eliminates Verilog testbench race conditions via VPI callbacks. It falls back to iVerilog with `$display` testbenches if cocotb isn't installed.
What Verilog patterns does the pipeline support?
The coder sub-agent includes 5 inline mini-patterns: FSM (three-block), hash/crypto rounds, pipeline registers, handshake logic, and barrel shifters. These give the LLM concrete register-transfer skeletons to adapt for your design.
How long does a design run take?
Depends on design complexity. Simple 32-bit ALU: 5–10 minutes. Medium designs (256-bit hash): 15–30 minutes. Complex pipelines: 30+ minutes. Stage 2 (codegen) and Stage 4 (lint/synth) run sub-agents in parallel to save time.
What if my design fails verification?
The pipeline logs all failures to `logs/` with detailed waveform analysis (`wave_diff.txt`, `wave_table.txt`) and timing diagnostics. Use these to understand the bug before manually fixing or providing design clarifications in Step 0.

Glossary

RTL (Register-Transfer Level)
Hardware description abstraction that specifies data movement between registers and combinational logic operations. The input format for synthesis tools like Yosys.
Golden Model
A high-level reference implementation (usually in Python) that specifies the correct behavior of a design. Used to validate RTL against the spec and generate expected test outputs.
Synthesis
The automated process of converting RTL code into a gate-level netlist. Yosys performs this conversion and reports area, timing, and resource usage.
VCD (Value Change Dump)
A standard waveform file format used by simulators to record signal transitions over time. Used for debugging and waveform analysis.
Sub-Agent
A specialized Claude Code session that handles a specific task (e.g., RTL code generation, linting) under the control of the main orchestration session.

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